A typical example of the decoder unit is illustrated in FIG. 1 and largely comprises a NOR gate 1 consisting of a plurality of n-channel MOS type field effect transistors 2, 3 and 4 coupled in parallel between an output node 5 and a ground node 6, a precharging transistor 7 formed by an n-channel MOS type field effect transistor coupled between a source of positive supply voltage level Vcc and the output node 5, an output transistor 8 formed by an n-channel MOS type field effect transistor with a gate electrode capable of being electrically coupled to the output node 5 of the NOR gate 1, and an n-channel MOS type field effect transistor 9 capable of transferring a voltage level at the output node 5 to the gate electrode of the output transistor 8. The precharging transistor 7 has a gate electrode where a precharging signal Sp of active high voltage level H1 appears prior to a decoding operation, so that the output node 5 is charged up to a positive high voltage level H2 lower than the positive supply voltage level Vcc by a threshold voltage Vth of the precharging transistor 7. All of the n-channel MOS type field effect transistors 2, 3 and 4 have respective gate electrodes where data bits B0 to Bm of an input signal Sin respectively appear upon the decoding operation, then the output node 5 has a voltage level of either high or low voltage level due to switching operations of the n-channel MOS type field effect transistors 2, 3 and 4. The voltage level at the output node 5 is transferred through the n-channel MOS type field effect transistor 9 to the gate electrode of the output transistor 8, and the output transistor 8 is supplied with a driving signal Sdv, so that the voltage level at a decoding node 10 reflects a result of the decoding operation carried out by the NOR gate 1.
The decoding operation of the prior-art decoder unit is hereinunder described in detail with reference to FIGS. 2A and 2B. Prior to the decoding operation, the precharging signal Sp is in the active high voltage level H1 so as to allow the precharging transistor 7 to turn on, thereby charging up the output node 5 to the positive high voltage level H2. After the precharging operation for the output node 5, the precharging signal Sp goes down to the ground level at time t1. Assuming now that at least one data bit B0 of the input signal Sin is in a positive high voltage level H3 corresponding to logic "1" level as seen in FIG. 2A, one of the n-channel MOS type field effect transistors 2 to 4 turns on to provide a conduction path between the output node 5 and the ground node 6, so that the output node 5 is discharged to the ground level at time t2. The output node 5 of the ground level causes the output transistor 8 to remain in the off state, so that the decoding node 10 keeps the ground level even if the driving signal Sdv goes up to the positive high voltage level at time t3. The precharing signal Sp goes up to the positive high voltage level again for the subsequent decoding operation at time t5.
On the other hand, if the input signal Sin consists of the data bits of the ground levels as shown in FIG. 2B, the output node 5 remains in the positive high voltage level H2 upon application of the input signal Sin. The positive high voltage level at the output node 5 is transferred to the gate electrode of the output transistor 8 through the n-channel MOS type field effect transistor 9 applied with the positive supply voltage level Vcc, and, for this reason, the output transistor 8 turns on to provide a conduction path to the decoding node 10. At time t3, the driving signal Sdv goes up to the positive high voltage level, then the decoding node 10 follows the driving signal Sdv with a delay and reaches the positive high voltage level at time t4. The precharging signal Sp goes up to the positive high voltage level at time t5 as similar to the above mentioned decoding operation. Thus, the prior-art decoding unit carries out the decoding operation on the input signal Sin.
However, a problem is encountered in the prior-art decoding unit in mis-decoding operation due to unusual voltage level at the output node 5. In detail, if the output node 5 goes up to an extremely high voltage level Hhh larger than the sum of the supply voltage level Vcc and the threshold voltage level Vth due to, for example, an electrostatic induction as shown in FIG. 2C, the decoding node 10 tends to remain in a positive voltage level H4 larger than a threshold voltage of a component transistor even if one of the data bit B0 is in the positive high voltage level H3. If one of the data bit is in the positive high voltage level H3, the decoding node 10 should remain in the ground level as shown in FIG. 2A. This means that a mis-decoding operation takes place in the decoding unit. If the decoding unit is incorporated in an address decoder of a memory device together with other decoder units, the mis-decoding operation causes the address decoder to specify a plurality of addresses or produce a multi-selection. The multi-selection is liable to take place in the address decoder upon application of the input signal Sin with only one logic "1" bit.
Another prior art decoder unit is illustrated in FIG. 3 and largely comprises a NOR gate 21 consisting of a plurality of n-channel MOS type field effect transistors 22, 23 and 24 coupled in parallel between an output node 25 and a reference node 26, a precharging transistor 27 formed by an n-channel MOS type field effect transistor coupled between a source of positive supply voltage level Vcc and the output node 25, an output transistor 28 formed by an n-channel MOS type field effect transistor with a gate electrode capable of being electrically coupled to the output node 25 of the NOR gate 21, an n-channel MOS type field effect transistor 29 capable of transferring a voltage level at the output node 25 to the gate electrode of the output transistor 28, and a series combination of n-channel MOS type field effect transistors 30 and 31 coupled between the source of positive supply voltage level Vcc and the ground node 26. The decoder unit illustrated in FIG. 3 is basically similar in circuit behavior to that in FIG. 1 except for the function of the series combination of the n-channel MOS type field effect transistors 30 and 31. The reference node 26 is provided between the n-channel MOS type field effect transistors 30 and 31, so that the NOR gate 21 is activated with a control signal Scn applied to a gate electrode of the n-channel MOS type field effect transistor 31. However, the output node 25 is merely coupled to the source of positive supply voltage level Vcc, then the same problem is encountered in the prior-art decoder unit illustrated in FIG. 3.